This application relates to ferroelectric thin films which are used in nonvolatile memories and specifically to a shallow junction metal-ferroelectric-metal-silicon semi-conductor. Known ferroelectric random access memories (FRAM) are constructed with one transistor (1T) and one capacitor (1C). The capacitor is generally made by sandwiching a thin ferroelectric film between two conductive electrodes, which electrodes are usually made of platinum. The circuit configuration and the read/write sequence of this type of memory are similar to that of conventional dynamic random access memories (DRAM), except that no data refreshing is necessary in a FRAM. Known FRAMs have a fatigue problem that has been observed in the ferroelectric capacitor, which is one of the major obstacles that limit the viable commercial use of such memories. The fatigue is the result of a decrease in the switchable polarization (stored nonvolatile charge) that occurs with an increased number of switching cycles. As used in this case, "switching cycles" refers to the sum of reading and writing pulses in the memory.
Another known use of ferroelectric thin films in memory applications is to form a ferroelectric-gate-controlled field effect transistor (FET) by depositing the ferroelectric thin film directly onto the gate area of the FET. Such ferroelectric-gate controlled devices have been known for some time and include devices known as metal-ferroelectric-silicon (MFS) FETs. FRAMs incorporating the MFS FET structure have two major advantages over the transistor-capacitor configuration: (1) The MFS FET occupies less surface area, and (2) provides a non-destructive readout (NDR). The latter feature enables a MFS FET device to be read thousands of times without switching the ferroelectric polarization. Fatigue, therefore, is not a significant concern when using MFS FET devices. Various forms of MFS FET structures may be constructed, such as metal ferroelectric insulators silicon (MFIS) FET, metal ferroelectric metal silicon (MFMS) FET, and metal ferroelectric metal oxide silicon (MFMOS) FET.
There are a number of problems that must be overcome in order to fabricate an efficient MFS FET device. The first problem is that it is difficult to form an acceptable crystalline ferroelectric thin film directly on silicon. Such structure is shown in U.S. Pat. No. 3,832,700. Additionally, it is very difficult to have a clean interface between the ferroelectric material and the silicon. Further, there is a problem retaining an adequate charge in the ferroelectric material. A FEM structure on a gate region is shown in U.S. Pat. No. 5,303,182, which emphasizes that the transfer of metal ions into the gate region is undesirable. Similar structure is shown in U.S. Pat. No. 5,416,735.
It is an object of this invention to overcome the aforementioned problems.
Another object of the invention is to provide an MFS FET device which provides a non-destructive readout.
Yet another object of the invention to provide an MFS FET device that occupies a relatively small surface area.
A further object of the invention is to provide an MFS FET device which requires a relatively low programming voltage.
Yet another object of the invention is to provide an FEM gate unit which has an asymmetric ferroelectric polarization.
The method of the invention includes forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a silicon substrate, with doping impurities of a first type to form a conductive substrate of a first type, implanting doping impurities of a second type in the conductive substrate of the first type to form a conductive channel of a second type, implanting doping impurities of a third type in the conductive channel of the second type to form a conductive channel of a third type for use as a gate junction region, implanting doping impurities of a fourth type on either side of the gate junction region to form plural conductive channels of a fourth type for use as a source junction region and a drain junction region; and depositing an FEM gate unit over the gate junction region.
The ferroelectric memory cell of the invention includes a silicon substrate of a first conductive type, a well structure of a second conductive type formed in the substrate, a sub-well structure of a third conductive type formed in the well structure, for use as a gate junction region. A source junction region and a drain junction region are located in the sub-well on either side of the gate junction region, along with a program line region, all doped to form conductive channels of a fourth type. A FEM gate unit overlays the conductive channel of the third type. An insulating layer overlays the junction regions, the FEM gate unit and the substrate. Suitable electrodes are connected to the various active regions in the memory cell.
These and other objects and advantages of the invention will become more fully apparent as the description which follows is read in conjunction with the drawings.